1. Field of the Invention
The present invention relates generally to a semiconductor memory device and, more particularly, to a sense amplifier for use in a DRAM semiconductor device that provides local isolation and pre-charge circuits.
2. Description of the Related Art
An increasing number of electronic equipment and electronic-based systems require some form of high-speed memory devices for storing and retrieving information (or xe2x80x9cdataxe2x80x9d). While the types of such memory devices vary widely, semiconductor memory devices are most commonly used in memory applications requiring implementation in a relatively small area. Within this class of semiconductor memory devices, the DRAM (Dynamic Random Access Memory) is one of the more commonly used types.
The DRAM has memory arrays consisting of a number of intersecting row and column lines of individual transistors or memory cells. In a conventional dynamic random access memory (DRAM) device each memory cell, or memory bit, consists of one transistor and one capacitor. A terminal of the transistor is connected to a digit line, or bitline, of the memory device. Another terminal of the transistor is connected to a terminal of the capacitor and the gate terminal of the transistor is connected to a wordline of the memory device. The transistor thus acts as a gate between the digit line and the capacitor.
The second terminal of the capacitor is connected to a voltage rail which carries a voltage, such as Vcc/2. Thus, when the wordline for a particular cell is active, the gate transistor is in a conducting state and the capacitor is connected to the digit line. The capacitor stores a charge that, depending on whether the capacitor is charged or discharged, represents either a logic high or a logic low value.
Typically, a microcomputer circuit selects (or activates) particular row and column lines to access selected memory cells. xe2x80x9cAccessxe2x80x9d typically refers to reading data from or writing data to selected memory cells. Reading data from the memory cells involves the use of a sense amplifier to detect whether the voltage level stored in the memory cell represents a binary one (logic high) or a binary zero (logic low).
Memory devices are typically constructed with complementary digit lines of equal capacitance. Sense amplifiers are connected between the digit lines and operate to sense the differential voltage across the digit lines. Before a memory cell is selected for access, the complementary digit lines must be equilibrated. Equilibration circuits typically short the complementary digit lines together, resulting in an equilibrate voltage equal to the voltage midpoint between the two equal capacitance and logically opposite digit lines. Conventionally, a DRAM contains one sense amplifier for a designated group (row or column) of memory cells. If the voltage level stored in the memory cell represents a binary zero, after the sense amplifier is activated, one of the digit lines will increase in level, typically to a supply voltage Vcc, and the other digit line will decrease in level, typically to a ground level. If the voltage level stored in the selected memory cell corresponds to a binary one, a change in the opposite direction occurs. Through this complementary operation, the sense amplifier yields a single output signal which is coupled through an output buffer to an output pin of the DRAM device.
FIG. 1 illustrates a sense amplifier 10 of a DRAM device having a first array ARRAY020 and a second array ARRAY122, each of which comprises a plurality of memory cells 21 (shown in ARRAY020). As is generally known in the art, the term sense amplifier includes a collection of circuit elements connected to the digit lines of a DRAM array. This collection typically includes isolation transistors, devices for equilibration and bias, one or more N-sense amplifiers, one or more P-sense amplifiers, and devices connecting selected digit lines to input/output signal lines as will be described below.
As shown in FIG. 1, sense amplifier 10 includes a P-sense amplifier 70 and an N-sense amplifier 80 for sensing charge stored in the selected memory cell of the selected array 20, 22 via a voltage differential on the pair of digit lines D024 and D0* 26. One of the arrays 20, 22 is selected by application of signals ISOa and ISOb to transistors 32a, 32b and 34a, 34b, respectively. Thus, when ISOa is driven to a logic high value and ISOb is driven to a logic low value, transistors 32a and 32b become conductive, i.e., turn on, to connect ARRAY020 to P-sense amplifier 70 and N-sense amplifier 80 while transistors 34a and 34b do not conduct, i.e., turn off, to isolate ARRAY122 from P-sense amplifier 70 and N-sense amplifier 70. When ISOa is driven to a logic low value and ISOb is driven to a logic high value, transistors 34a and 34b turn on to connect ARRAY122 to P-sense amplifier 80 and N-sense amplifier 70 while transistors 32a and 32b turn off to isolate ARRAY020 from P-sense amplifier 80 and N-sense amplifier 70.
Equilibration circuits 50a and 50b are provided to equilibrate the digit lines D024 and D0* 26. Equilibration circuit 50a includes transistor 54 with a first source/drain region coupled to digit line D024, a second source/drain region coupled to digit line D0* 26 and a gate coupled to receive an equilibration signal EQa. Equilibration circuit 50a further includes first and second transistors 56 and 58. Transistor 56 includes a first source/drain region that is coupled to digit line D024, a gate that is coupled to receive the equilibration signal EQa and a second source/drain region that is coupled to receive an equilibration voltage Veq, which is typically equal to Vcc/2. Second transistor 58 includes a first source/drain region that is coupled to digit line D0* 26, a gate that is coupled to receive the equilibration signal EQa and a second source/drain region that is coupled to the equilibration voltage Veq. When the signal EQa is at a high logic level, equilibration circuit 50a effectively shorts digit line D024 to digit line D0* 26 such that both lines are equilibrated to the voltage Veq. Equilibration circuit 50b is constructed in a similar manner to equilibration circuit 50a and operates when the EQb signal is at a high logic level.
When P-sense amplifier 70 and N-sense amplifier 80 have sensed the differential voltage across the digit lines D024 and D0* 26 (as described below), a signal representing the charge stored in the accessed memory cell is output from the DRAM device on the input/output (I/O) lines I/O 36 and I/O* 38 by connecting the I/O lines I/O 36 and I/O* 38 to the digit lines D024 and D0* 26, respectively. A column select (CSEL) signal is applied to transistors 40, 42 to turn them on and connect the digit lines D024 and D0* 26 to the I/O lines I/O 36 and I/O* 38.
The operation of the P-sense amplifier 80 and N-sense amplifier 70 is as follows. These amplifiers work together to detect the access signal voltage and drive the digit lines D024 and D0* 26 to Vcc and ground accordingly. As shown in FIG. 1, the N-sense amplifier 80 consists of cross-coupled NMOS transistors 82, 84 and drives the low potential digit line to ground. Similarly, the P-sense amplifier 70 consists of cross-coupled PMOS transistors 72, 74 and drives the high potential digit line to Vcc. The NMOS pair 82, 84 or N-sense-amp common node is labeled RNL*. Similarly, the P-sense-amp 70 common node is labeled ACT (for ACTive pull-up). Initially, RNL* is biased to Vcc/2 and ACT is biased to ground. Since the digit line pair D024 and D0* 26 are both initially at Vcc/2 volts, the N-sense-amp transistors 82, 84 remain off due to zero Vgs potential. Similarly, both P-sense-amp transistors 72, 74 remain off due to their negative Vsg potential. As discussed in the preceding paragraph, a signal voltage develops between the digit line pair 24, 26 when the memory cell access occurs. While one digit line contains charge from the cell access, the other digit line serves as a reference for the sensing operation. The sense amplifier firing generally occurs sequentially rather than concurrently. The N-sense-amp 80 fires first and the P-sense-amp 70 second. Dropping the RNL* signal toward ground will fire the N-sense-amp 80. As the voltage between RNL* and the digit lines approaches Vt, the NMOS transistor whose gate connection is to the higher voltage digit line will begin to conduct. Conduction results in the discharge of the low voltage digit line toward the RNL* voltage. Ultimately, RNL* will reach ground, bringing the digit line with it. Note that the other NMOS transistor will not conduct since its gate voltage derives from the low voltage digit line, which is discharging toward ground.
Shortly after the N-sense-amp 80 fires, ACT will be driven toward Vcc. This activates the P-sense-amp 70 that operates in a complementary fashion to the N-sense-amp 80. With the low voltage digit line approaching ground, a strong signal exists to drive the appropriate PMOS transistor into conduction. This will charge the high voltage digit line toward ACT, ultimately reaching Vcc. Since the memory bit transistor remains on during sensing, the memory bit capacitor will charge to the RNL* or ACT voltage level. The voltage, and hence charge, which the memory bit capacitor held prior to accessing will restore a full level, i.e., Vcc for a logic one and GND for a logic zero.
There are problems, however, with the sense amplifier circuitry as illustrated in FIG. 1. As is well-known, integrated circuit memories are generally mass produced by fabricating hundreds of identical circuit patterns on a single semiconducting wafer. Each wafer is subsequently cut into hundreds of identical dies or chips. The advantages of building integrated circuits with smaller individual circuit elements are well known: more and more circuitry may be fabricated on a single chip, electronic equipment may become less bulky, reliability is improved by reducing the number of solder or plug connections, assembly and packaging costs are minimized, circuit performance may improve and higher clock speeds become feasible. For integrated circuit memories there are some disadvantages. As the size of the individual cell is reduced, the size of the individual electrical components in the cell and the strength of the electrical signals associated with them is also reduced. As the number of individual storage cells on a single chip is increased, the length of the digit lines connecting cells to sense amplifiers becomes longer. The capacitance associated with each digit line becomes large in comparison to the capacitance of a memory cell. Hence, the signals transferred to the digit line from an individual storage cell or I/O lines become weaker and the time for developing a useful signal level on a digit line will increase. As is well known, speed is an important factor in such memories. The faster the cells can be read and written, the faster the associated computer circuit of which the memory may be a part can operate, and the more functions the computer can adequately perform. There remains a need for a memory architecture that allows fast write cycles.
The present invention alleviates the problems associated with the prior art and provides a sense amplifier circuit that decreases the write cycle, row to column time (tRCD) and precharge time (tRP) by locally isolating the digit lines from the N-sense and P-sense amplifier circuits and pre-charging the isolated digit lines.
In accordance with the present invention, a local isolation device is provided between the N-sense amplifier and the digit lines of a memory array. Similarly, a local isolation device is provided between the P-sense amplifier and the digit lines of the memory array. The local isolation devices are controlled by the inversion phase during the on state of the column select signal. Additionally, a local pre-charge circuit is provided to pre-charge the isolated digit lines to a voltage potential, such as for example Vcc. The local isolation and pre-charging of the digit lines provides for a faster write cycle, faster pre-charge time and faster row to column time.
These and other advantages and features of the invention will become more readily apparent from the following detailed description of the invention which is provided in connection with the accompanying drawings.